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Micrel
Programming
General
The MICRF505 functions are enabled through a
number of programming bits. The programming bits
are organized as a set of addressable control
registers, each register holding 8 bits.
There are 23 control registers in total in the
MICRF505, and they have addresses ranging from 0
to 22. The user can read all the control registers.
The user can write to the first 22 registers (0 to 21);
the register 22 is a read-only register.
All control registers hold 8 bits and all 8 bits must be
written to when accessing a control register, or they
will be read. Some of the registers do not utilize all 8
bits. The value of an unused bit is “don’t care.”
The control register with address 0 is referred to as
ControlRegister0, the control register with address 1
is ControlRegister1 and so on. A summary of the
control registers is given in the table below. In
addition to the unused bits (marked with”-“) there are
a number of mandatory bits (marked with “0” or “1”).
Always maintain these as shown in the table.
Adr
MICRF505BML/YML
The control registers in MICRF505 are accessed
through a 3-wire interface; clock, data and chip
select. These lines are referred to as SCLK, IO, and
CS, respectively. This 3-wire interface is dedicated
to control register access and is referred to as the
control interface. Received data (via RF) and data to
transmit (via RF) are handled by the DataIXO and
DataClk (if enabled) lines; this is referred to as the
data interface.
The SCLK line is applied externally; access to the
control registers are carried out at a rate determined
by the user. The MICRF505 will ignore transitions on
the SCLK line if the CS line is inactive. The
MICRF505 can be put on a bus, sharing clock and
data lines with other devices.
All control registers should be written to after a
battery reset. During operation, it is sufficient to write
to one register only. The MICRF505 will
automatically enter power down mode after a battery
reset.
Data
A6…A0
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
D7
LNA_by
Modulation1
CP_HI
‘1’
Mod_F2
-
-
BitRate_clkS1
‘1’
‘0’
-
-
N0_7
-
M0_7
-
-
N1_7
-
M1_7
‘1’
-
FEE_7
D6
PA2
Modulation0
SC_by
‘1’
Mod_F1
-
Mod_clkS2
BitRate_clkS0
‘1’
‘0’
-
-
N0_6
-
M0_6
-
-
N1_6
-
M1_6
‘0’
-
FEE_6
D5
PA1
‘0’
‘0’
‘0’
Mod_F0
‘0’
Mod_clkS1
RefClk_K5
ScClk5
‘1’
A0_5
-
N0_5
-
M0_5
A1_5
-
N1_5
-
M1_5
‘1’
-
FEE_5
D4
PA0
‘0’
PA_By
VCO_IB2
Mod_I4
‘1’
Mod_clkS0
RefClk_K4
ScClk4
XCOtune4
A0_4
-
N0_4
-
M0_4
A1_4
-
N1_4
-
M1_4
‘1’
-
FEE_4
D3
Sync_en
RSSI_en
OUTS3
VCO_IB1
Mod_I3
Mod_A3
BitSync_clkS2
RefClk_K3
ScClk3
XCOtune3
A0_3
N0_11
N0_3
M0_11
M0_3
A1_3
N1_11
N1_3
M1_11
M1_3
‘0’
FEEC_3
FEE_3
D2
Mode1
LD_en
OUTS2
VCO_IB0
Mod_I2
Mod_A2
BitSync_clkS1
RefClk_K2
ScClk2
XCOtune2
A0_2
N0_10
N0_2
M0_10
M0_2
A1_2
N1_10
N1_2
M1_10
M1_2
‘1’
FEEC_2
FEE_2
D1
Mode0
PF_FC1
OUTS1
VCO_freq1
Mod_I1
Mod_A1
BitSync_clkS0
RefClk_K1
ScClk1
XCOtune1
A0_1
N0_9
N0_1
M0_9
M0_1
A1_1
N1_9
N1_1
M1_9
M1_1
‘0’
FEEC_1
FEE_1
D0
Load_en
PF_FC0
OUTS0
VCO_freq0
Mod_I0
Mod_A0
BitRate_clkS2
RefClk_K0
ScClk0
XCOtune0
A0_0
N0_8
N0_0
M0_8
M0_0
A1_0
N1_8
N1_0
M1_8
M1_0
‘1’
FEEC_0
FEE_0
Names of programming bits, unused bits (“-“) and mandatory bits (“1” or “0”) are shown. Change of mandatory bits may cause malfunction .
Table 1. Control Registers in MICRF505
October 2006
9
M9999-103106
+1 408-944-0800
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